Combinational Logic Circuits


 Letitia Cox
 3 years ago
 Views:
Transcription
1 Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung)
2 Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization 25 Map Manipulation 26 MultipleLevel Circuit Optimization 27 Other Gate Types 28 ExclusiveOR Operator and Gates 29 HighImpedance Outputs 210 Chapter Summary J.J. Shann 22
3 21 Binary Logic and Gates Digital circuits: hardware components that manipulate binary information are implemented using transistors and interconnections in integrated circuits. Logic gate: basic ckt that performs a specific logical op J.J. Shann 23
4 A. Binary Logic Binary logic: deals w/ binary variables and the ops of a special form of mathematical logic (called boolean algebra) applied to these variables. binary variable: variable that take on two discrete values resembles binary arithmetic, but should no be confused w/ each other: When we talk about logic, everything is bitwise or true/false; bits do not associate w/ each other to mean magnitude When we talk about arithmetic, some group of bits are now treated as representing a magnitude J.J. Shann 24
5 Basic Logic Operations Basic logical ops: p.31, Table 21 AND:, identical to binary multiplication OR:, resemble binary addition In binary logic, In binary arithmetic: NOT: complement;, J.J. Shann 25
6 Truth Table Truth table: a table of combinations of the binary variables showing the relationship b/t the values that the variables take on and the values of the result of the op. 2 n rows, n: # variables E.g.: truth table for AND op J.J. Shann 26
7 B. Logic Gates Logic gate: is an electronic ckt that operate on one or more input signals to produce an output signal. The input terminals of logic gates accept binary signals within the allowable range and respond at the output terminals w/ binary signals that fall within a specified range. E.g.: transition region indeterminate region J.J. Shann 27
8 Graphic symbols of 3 basic logic gates: Timing diagram: This diagram has little to do with timing; I prefer to call it I/O voltage relationship diagram J.J. Shann 28
9 Multipleinput logic gates: AND and OR gates may have 2 inputs. E.g.: J.J. Shann 29
10 22 Boolean Algebra Boolean algebra: is an algebra dealing w/ binary variables and logic ops binary variables: are designated by letters of the alphabet logic ops: AND, OR, NOT Boolean expression: an algebraic expression formed by using binary variables, the constants 0 and 1, the logic op symbols, and parentheses. e.g.: ( Y Z) Z 1 J.J. Shann 210
11 Boolean Function Boolean function: can be described by a Boolean equation, a truth table, or a logic ckt diagram Singleoutput Boolean function Multipleoutput Boolean function Every output should be treated independently; so this in effect is composed of many singleoutput boolean functions J.J. Shann 211
12 Boolean Equation Boolean equation: consists of a binary variable identifying the function followed by an equal sign and a Boolean expression. expresses the logical relationship b/t binary variables can be expressed in a variety of ways E.g.: F(, Y, Z) YZ YZ WYZ WY WYZ literals YZ terms J.J. Shann 212
13 Truth Table Truth table for a function: is unique a list of all combinations of 1 s and 0 s that can be assigned to the binary variables and a list that shows the value of the function for each binary combination. E.g.: F (, Y, Z) YZ J.J. Shann 213
14 Logic Circuit Diagram Logic circuit diagram: An algebraic expression for a Boolean function Can be mapped to a ckt diagram composed of logic gates Circuit gates are interconnected by wires that carry logic signals. E.g.: F (, Y, Z) YZ Combinational logic circuits J.J. Shann 214
15 A. Basic Identities of Boolean Algebra Basic identities of Boolean Algebra:, Y, Z: binary variable (Note similarities between formulas on the same row) J.J. Shann 215
16 Duality Principle Dual: The dual of an algebraic expression is obtained by interchanging OR and AND ops and replacing 1 s by 0 s and 0 s by 1 s (OR AND, 0 1) E.g.: dual Duality principle: 0 1 A Boolean equation remains valid if we take the dual of the expressions on both sides of the equals sign. E.g.: J.J. Shann 216
17 Verification of Identities Verification of an identity: by truth table or verified identities E.g.: 0 (eq. 1) Case 1: 0, Case 2: 1, E.g.: DeMorgan s theorem ( Y) Y (eq. 16) J.J. Shann 217
18 General DeMorgan s Theorem DeMorgan s theorem: Y Y Y Y General DeMorgan s theorem: n 1 n n 1 n J.J. Shann 218
19 B. Algebraic Manipulation Simplification of Boolean functions: Boolean algebra is a useful tool for simplifying digital ckts. E.g.: F YZ YZ Z F YZ YZ Z Y ( Z Z ) Z 14 : x( y z) xy xz Y 1 Z 7 : x x 1 Y Z 2 : x 1 x J.J. Shann 219
20 F YZ YZ Y Z Z J.J. Shann 220
21 Implementing Boolean Equations When a Boolean equation is implemented w/ logic gates: each term requires a gate each variable within the term designates an input to the gate literal: a single variable within a term that may or may not be complemented E.g.: F YZ YZ Z 3 terms & 8 literals 2 terms & 4 literals F Y Z * Reduce # of terms, # of literals, or both in a Boolean expression is often possible to obtain a simpler ckt J.J. Shann 221
22 Reducing Expressions by Boolean Algebra Boolean algebra may be applied to reduce an expression for obtaining a simpler ckt: Aside: there are Computer tools for synthesizing logic ckt Manual method: cutandtry E.g.s: i. ii. iii. iv. v. vi. Y ( ( ( Y Y Y Y ) Y )( (1 Y ) ( Y ) ( Y )( Y ) Y ) Y Y Y ) dual YY Y Y J.J. Shann 222
23 C. Complement of a Function Complement of a function F: interchange of 1 s to 0 s and 0 s to 1 s for the values of F in the truth table, or can be derived algebraically by applying DeMorgan s theorem interchange AND and OR ops and complement each variable and constant, or Y Y Y Y take the dual of the function equation and complement each literal: OR AND, 0 1 (Last two methods exemplified below on following two pages) J.J. Shann 223
24 J.J. Shann 224 Examples Complementing functions by applying DeMorgan s theorem: E.g.s: YZ YZ F 1 ) ( ) ( ) ( ) ( ) ( 1 Z Y Z Y YZ YZ YZ YZ F ) ( 2 YZ YZ F ) ( ) ( ) ( ) ( ) ( )) ( ( 2 Z Y Z Y YZ Z Y YZ Z Y YZ Z Y F Y Y Y Y
25 J.J. Shann 225 Complementing functions by using duals: E.g.s: (dual: OR AND, 0 1) ) ( ) ( each literal complement ) ( ) ( of dual F Z Y Z Y Z Y Z Y F YZ YZ F ) ( ) ( each literal complement ) ( ) ( of dual ) ( F Z Y Z Y Z Y Z Y F YZ YZ F
26 23 Standard Forms Standard forms of Boolean expressions: Contain sum of product terms & product of sum terms Two types: sumofproducts form (product term) (product term) productofsums form (sum term) (sum term) Product term: a logical product (AND) among literals E.g.: Y Z Sum terms a logical sum (OR) among literals E.g.: YZ J.J. Shann 226
27 A. Minterms and Maxterms Minterm: m j a product term in which all the variables appear exactly once, either complemented or uncomplemented represents exactly one combination of the binary variables in a truth table A literal is a complemented variable if the corresponding bit of the related binary combination is 0 and is an uncomplemented variable if it is 1. This combination makes the corresponding minterm true, and all other minterms false There are 2 n distinct minterms for n variables. Symbol: m j, j: denotes the decimal equivalent of the binary combination for which the minterm has the value 1 E.g.: Minterms for 3 variables J.J. Shann 227
28 E.g.: Minterms for 3 variables * A literal is a complemented variable if the corresponding bit of the related binary combination is 0 and is an uncomplemented variable if it is 1. J.J. Shann 228
29 Maxterms Maxterm: M j a sum term that contains all the variables in complemented or uncomplemented form represents exactly one combination of the binary variables in a truth table A literal is a uncomplemented variable if the corresponding bit of the related binary combination is 0 and is an complemented variable if it is 1. has the value 0 for that combination and 1 for all others There are 2 n distinct maxterms for n variables. Symbol: M j, j: denotes the decimal equivalent of the binary combination for which the maxterm has the value 0 E.g.: Maxterms for 3 variables J.J. Shann 229
30 E.g.: Maxterms for 3 variables * A literal is a uncomplemented variable if the corresponding bit of the related binary combination is 0 and is an complemented variable if it is 1. J.J. Shann 230
31 Minterms vs. Maxterms A minterm a function, not equal to 0, having the min # of 1 s in its row in the truth table (see p. 28) A maxterm a function, not equal to 1, having the max # of 1 s in its row in the truth table (see p.30 M j (m j ) E.g.: For 3 variables & j 3 m 3 YZ m YZ Y Z 3 M 3 J.J. Shann 231
32 Representing Boolean Function by m j s or M j s Given the truth table of a function a Boolean function in sum of minterms or in product of maxterms Sum of minterms: a logical sum of all the minterms that produce a 1 in the function. Product of maxterms: a logical product of all the maxterms that produce a 0 in the function. J.J. Shann 232
33 E.g.: Represent F and F in sumofminterms form F Y Z Y Z YZ YZ m 0 m 2 m 5 m 7 m(0,2,5,7) F YZ YZ Y Z Y Z m 1 m3 m4 m6 m(1,3,4,6) J.J. Shann 233
34 J.J. Shann 234 E.g.: Represent F in productofmaxterms form ),,, M( Z Y Z Y Z Y Z Y M m M M M M m m m m m m m m F j j ) )( )( )( ( ) ( ) (1,3,4,6 ),, ( m Z Y F
35 Conversion of SoP to Sumofminterms Form Conversion: by means of truth table or Boolean algebra E Y Z Method 1: by truth table E.g.:Convert to sumofminterms form E Y Z truth table m(0,1,2,4,5 ) J.J. Shann 235
36 E.g.:Convert E Y Z to sumofminterms form Method 2: by Boolean algebra E Y Z Y ( )( Z Z ) Z( Y Y ) YZ YZ YZ YZ YZ YZ YZ YZ YZ YZ YZ m(0,1,2,4,5) J.J. Shann 236
37 Summary of the Properties of Minterms There are 2 n minterms for n Boolean variables. These minterms can be regarded as from 0 to 2 n 1. Any Boolean function can be expressed in sum of minterms. The complement of a function contains those minterms not included in the original function. A function that includes all the 2 n minterms is equal to logic 1. E.g.: G(, Y) Σm(0,1,2,3) 1 J.J. Shann 237
38 Summary of the Properties of Maxterms There are 2 n maxterms for n Boolean variables. These maxterms can be regarded as from 0 to 2 n 1. Any Boolean function can be expressed in product of maxterms. The complement of a function contains those maxterms not included in the original function. A function that includes all the 2 n maxterms is equal to logic 0. E.g.: G(, Y) ΠM(0,1,2,3) 0 J.J. Shann 238
39 B. Sum of Products (SoP) Sumofproducts form: a standard form that contains product terms w/ any number of literals. These AND terms are ORing together. E.g.: F (, Y, Z) Y Y Z Y Sumofminterms form: is a special case of SoP form is obtained directly from a truth table contains the max # of literals in each term and usually has more product terms than necessary simplify the expression to reduce the # of product terms and the # of literals in the terms a simplified expression is in sumofproducts form J.J. Shann 239
40 Logic Diagram for an SoP form Logic diagram for an SoP form: consists of a group of AND gates followed by a single OR gate. 2level implementation or 2level ckt Assumption: The input variables are directly available in their complemented and uncomplemented forms. ( Inverters are not included in the diagram) E.g.: F Y Y Z Y J.J. Shann 240
41 C. Product of Sums (PoS) Productofsums form: a logical product of sum terms & each logical sum term may have any # of distinct literals. 2level gating structure Special case: Productofmaxterms form E.g.: F ( Y Z) ( Y Z ) J.J. Shann 241
42 D. Nonstandard Form Nonstandard form: E.g.: F AB C(D E) 3level Nonstandard form Standard form: By using the distributive laws E.g.: F AB C(D E) AB CD DE 2level Standard form vs Nonstandard form J.J. Shann 242
43 24 TwoLevel Circuit Optimization Representation of a Boolean function: Truth table: unique Algebraic expression: many different forms digital logic circuit Minimization of Boolean function: Algebraic manipulation: literal minimization ( 22) use the rules and laws of Boolean algebra Disadv.: It lacks specific rules to predict each succeeding step in the manipulation process. Map method: gatelevel minimization ( 24~25) a simple straightforward procedure using Karnaugh map (Kmap) Disadv.: Maps for more than 4 variables are not simple to use. * The simplest algebraic expression: not unique J.J. Shann 243
44 A. Cost Criteria Two cost criteria: i. Literal cost the # of literal appearances in a Boolean expression ii. Gate input cost ( ) the # of inputs to the gates in the implementation iii. Analyses and comparison to follow J.J. Shann 244
45 Literal Cost Literal cost: the # of literal appearances in a Boolean expression E.g.: F F Adv.: is very simple to evaluate by counting literal appearances Disadv.: does not represent ckt complexity accurately in all cases E.g.: G G ( A AB C( D AB CD ABCD B)( B E) CE ABCD C)( C 5 literals 6 literals 8 literals D)( D A) 8 literals J.J. Shann 245
46 Gate Input Cost Gate input cost: the # of inputs to the gates in the implementation For SoP or PoS eqs, the gate input cost can be found by the sum of all literal appearances the # of terms excluding terms that consist only of a single literal the # of distinct complemented single literals (optional) E.g.: p.251 G ABCD ABCD G ( A B)( B C)( C 8 2 ( D)( D 8 4 ( is a good measure for contemporary logic implementation A) is proportional to the # of transistors and wires used in implementing a logic ckt. (especially for ckt 2 levels) 4) gate input counts 4) J.J. Shann 246
47 B. The Map Method Map method: Karnaugh map simplification a simple straightforward procedure Kmap: a pictorial form of a truth table a diagram made up of squares Each square represents one minterm of the function. Any adjacent squares in the map differ by only one variable. The simplified expressions produced by the map are always in one of the two standard forms: SOP (sum of products) if you work with 1s, or POS (product of sums) if you work with 0s J.J. Shann 247
48 (a) TwoVariable Map Twovariable map: 4 squares, one for each minterm. A function of 2 variables can be represented in the map by marking the squares that correspond to the minterms of the function. F(,Y) * Any adjacent squares in the map differ by only one variable. J.J. Shann 248
49 Example E.g.: <Ans> F 1 (,Y) F 2 m 1 m 2 m 3 m 3 Y Y Y Y Y ( Y Y ) Y ( )( Y ) Y J.J. Shann 249
50 (b) ThreeVariable Map Threevariable map: 8 minterms 8 squares F(,Y,Z) Only one bit changes in value from one adjacent column to the next Any two adjacent squares in the map differ by only one variable, which is primed in one square and unprimed in the other. E.g.: m 5 & m 7 Note: Each square has 3 adjacent squares. The right & left edges touch each other to form adjacent squares. E.g.: m 4 m 0, m 5, m 6 J.J. Shann 250
51 Map Minimization of SOP Expression Basic property of adjacent squares: Any two adjacent squares in the map differ by only one variable: primed in one square and unprimed in the other E.g.: m 5 YZ, m7 YZ Any two minterms in adjacent squares that are ORed together can be simplified to a single product term after removal of the different variable. E.g.: m 5 m7 YZ YZ Z( Y Y ) Z J.J. Shann 251
52 Procedure of map minimization of SOP expression: i. A 1 is marked in each minterm that represents the function. ii. Find possible adjacent 2 k squares: 2 adjacent squares (i.e., minterms) remove 1 literal 4 adjacent squares (i.e., minterms) remove 2 literal 2 k adjacent squares (i.e., minterms) remove k literal The larger the # of squares combined, the less the # of literals in the product (AND) term. * It is possible & encouraged to use the same square more than once. J.J. Shann 252
53 Example 23 Simplify the Boolean function F(, Y, Z) Σm(2,3,4,5) <Ans.> F Y Y J.J. Shann 253
54 4minterm Product terms Product terms using 4 minterms: E.g.: F(, Y, Z) Σm(0,2,4,6) m 0 m 2 m 4 m 6 Y Z Y Z Y Z Y Z Z( Y Y ) Z( Y Y ) Z Z Z( ) Z J.J. Shann 254
55 E.g.: F(, Y, Z) Σm(0,1,2,3,6,7) J.J. Shann 255
56 Example 24 Simplify the Boolean function F F 1 <Ans.> (, Y, Z) 2 (, Y, Z) m(3,4,6,7) m(0,2,4,5,6) J.J. Shann 256
57 Nonunique Optimized Expressions There may be alternative ways of combining squares to product equally optimized expressions: E.g.: F(, Y, Z) m(1,3,4,5,6 ) F(, Y, Z) m(1,3,4,5,6 ) Z Z Y Z Z YZ J.J. Shann 257
58 Simplifying Functions not Expressed as Sumofminterms Form If a function is not expressed as a sum of minterms: How to apply the map method here? use the map to obtain the minterms of the function & then simplify the function E.g.: Given the Boolean function F Z Y YZ YZ <Ans.> F Z Y YZ YZ 1, 3 2, 3 5 3, m(1,2,3,5,7 ) Z Y J.J. Shann 258
59 (c) FourVariable Map Fourvariable map: 16 minterms 16 squares F(W,, Y, Z) Note: Each square has 4 adjacent squares. The map is considered to lie on a surface w/ the top and bottom edges, as well as the right and left edges, touching each other to form adjacent squares. E.g.: m 8 m 0, m 9, m 10, m 12 J.J. Shann 259
60 Example 25 Simplify the Boolean function F(W,, Y, Z) Σ(0,1,2,4,5,6,8,9,12,13,14) <Ans.> F Y W Z Z J.J. Shann 260
61 Example 26 Simplify the Boolean function F ( A, B, C, D) ABC BCD ABC <Ans.> ABCD F BD BC ACD J.J. Shann 261
62 Relationship b/t the # of adjacent squares and the # of literals in the term: Any 2 k adjacent squares, for k o, 1,, n, in an nvariable map, will represent an area that gives a term of n k literals. J.J. Shann 262
63 Maps for more than 4 variables are not as simple to use: Employ computer programs specifically written to facilitate the simplification of Boolean functions w/ a large # of variables. J.J. Shann 263
64 25 Map Manipulation When choosing adjacent squares in a map: Ensure that all the minterms of the function are covered when combining the squares. Minimize the # of terms in the expression. avoid any redundant terms whose minterms are already covered by other terms J.J. Shann 264
65 A. Essential Prime Implicants Implicant: A product term is an implicant of a function if the function has the value 1 for all minterms of the product term. Prime implicant: PI a product term obtained by combining the max. possible # of adjacent squares in the map Essential prime implicant: EPI, must be included in resultant simplified F function If a minterm in a square is covered by only one PI, that PI is said to be essential. Look at each square marked w/ a 1 and check the # of PIs that cover it. J.J. Shann 265
66 Example: p.257 Find the PIs and EPIs of the Boolean function F(, Y, Z) Σm(1,3,4,5,6) <Ans.> F(, Y, Z) m(1,3,4,5,6 ) Z Z Y Z Z YZ 4 PIs : Z, Z, Y, YZ 2 EPIs : Z ( m3), Z ( m6 ) J.J. Shann 266
67 Example Find the PIs and EPIs of the Boolean function F(A,B,C,D) Σ(0,2,3,5,7,8,9,10,11,13,15) <Ans.> 6 PIs: BD, B'D', CD, B'C, AD, AB' 2 EPIs: BD (m5), B'D' (m0) J.J. Shann 267
68 Example (Cont ) Find the PIs and EPIs of the Boolean function F(A,B,C,D) Σ(0,2,3,5,7,8,9,10,11,13,15) <Ans.> Nonessential 6 PIs: BD, B'D', CD, B'C, AD, AB' 2 EPIs: BD (m 5 ), B'D' (m 0 ) J.J. Shann 268
69 B. Finding the Simplified Expression Procedure for finding the simplified expression from the map: (SoP form) i. Determine all PIs. ii. The simplified expression is obtained from the logical sum of all the EPIs plus other PIs that may be needed to cover any remaining minterms not covered by the EPIs. There may be more than one expression that satisfied the simplification criteria. J.J. Shann 269
70 Example 27 Simplify the Boolean function F(A,B,C,D) Σ(1,3,4,5,6,7,12,14) <Ans.> PIs: A'D, BD', A'B EPIs: A'D (m 1, m 3 ), BD' (m 12, m 14 ) A D: m 1,m 3,m 5,m 7 ; BD : m 4,m 6,m 12,m 14 sorted: m 1, m 3, m 4, m 5, m 6, m 7, m 12, m 14 F AD BD J.J. Shann 270
71 Example 28 Simplify the Boolean function F(A,B,C,D) Σ(0,5,10,11,12,13,15) <Ans.> EPIs : ABCD BCD ABC ABC Combine PIs that contains m 15 ACD F ABCD BCD ABC ABC or ABD J.J. Shann 271
72 Selection Rule of Nonessential PIs Selection rule of Nonessential PIs: Minimize the overlap among PIs as much as possible. Make sure that each PI selected includes at least 1 minterm not included in any other PI selected. It results in a simplified, although not necessarily minimum cost, SoP expression. J.J. Shann 272
73 Example 29 Simplify the Boolean function F(A,B,C,D) Σm(0,1,2,4,5,10,11,13,15) <Ans.> EPI : AC F( A, B, C, D) AC ABD ABC ABD J.J. Shann 273
74 Example: p.274 Simplify the Boolean function F(A,B,C,D) Σ(0,2,3,5,7,8,9,10,11,13,15) <Ans.> AB CD 6 PIs: BD, B'D', CD, B'C, AD, AB' 2 EPIs: BD, B'D' EPIs: BD, B'D' m 0,m 2, m 5, m 7, m 8, m 10, m 13, m 15 ; missing m 3, m 9, & m 11 Combine PIs that contains m 3,m 9, m 11 (CD, B'C, AD, AB') F BD B'D' CD AD BD B'D' CD AB' BD B'D' B'C AD BD B'D' B'C AB' J.J. Shann 274 EPIs nonepis
75 C. ProductofSums (PoS) Optimization Approach 1: First obtain simplified F' in the form of sum of products Then apply DeMorgan's theorem F (F')' > F': sum of products F: product of sums Approach 2: combinations of the maxterms of F E.g.: i. A 0 is marked in each maxterm that represents the function. ii. Find possible adjacent 2 k squares and realize each set as a sum (OR) term, w/ variables being complemented. CD M 0 M 1 (ABCD)(ABCD') (ABC)(DD') ABC AB M 0 M 1 M 3 M 2 01 M 4 M 5 M 7 M 6 11 M 12 M 13 M 15 M M 8 M 9 M 11 M 10 J.J. Shann 275
76 Example 38 Simplify the Boolean function in (a) SoP and (b) PoS: F(A,B,C,D) Σm(0,1,2,5,8,9,10) <Ans.> (a) F B D B C A C D (b) Approach 1: F AB CD BD F ( F ) ( A B)( C D)( B D) Approach 2: Think in terms of maxterms J.J. Shann 276
77 Gate implementation: (a) F B D B C A C D (b) F ( A B)( C D)( B D) The implementation of a function in a standard form is said to be a twolevel implementation. Assumption: The input variables are directly available in their complement Inverters are not needed. Determine which form will be best for a function: GIC (gate input count)? J.J. Shann 277
78 D. Don tcare Conditions What is a Don t care condition: the unspecified minterms of a function is represented by an E.g.: A 4bit decimal code has 6 combinations which are not used. Due to Incompletely specified function: has unspecified outputs for some input combinations Simplification of an incompletely specified function: When choosing adjacent squares to simplify the function in the map, the s may be assumed to be either 0 or 1, whichever gives the simplest expression. An need not be used at all if it does not contribute to covering a larger area. J.J. Shann 278
79 Example 211 Simplify the Boolean function F (w,x,y,z) Σm(1,3,7,11,15) which has the don tcare conditions d (w,x,y,z) Σm(0,2,5). <Ans.> (a) SOP: F (w,x,y,z) yz w x Σm(0,1,2,3,7,11,15) F (w,x,y,z) yz w z Σm(1,3,5,7,11,15) (b) POS: F (w,x,y,z) z (w y) Σm(1,3,5,7,11,15) J.J. Shann 279
80 26 MultipleLevel Circuit Optimization 2level ckt optimization: can reduce the cost of combinational logic ckts Multilevel ckts: ckts w/ more than 2 levels There are often additional cost saving available objective of this optimization May accompany longer delay J.J. Shann 280
81 Example E.g.: G ABC ABD E ACF ADF <Ans.> 2level implementation: gateinput cost 17 Multilevel implementation: distributive law G ABC ABD E ACF ADF AB( C D) E AF( C D) ( AB AF)( C D) E A( B F)( C D) E J.J. Shann 281
82 J.J. Shann 282
83 Multiplelevel Optimization Multiplelevel ckt optimization (simplification): is based on the use of a set of transformations that are applied in conjunction w/ cost evaluation to find a good, but not necessarily optimum solution. J.J. Shann 283
84 Multilevel Optimization Transformations Transformations: Factoring: is finding a factored form from either a SoP or PoS expression for a function Decomposition: is the expression of a function as a set of new functions Extraction: is the expression of multiple functions as a set of new functions Substitution of a function G into a function F: is expressing F as a function of G and some or all of the original variables of F Elimination: flattening or collapsing is the inverse of substitution function G in an expression for function F is replaced by the expression for G J.J. Shann 284
85 J.J. Shann 285 A. Transformation for GIC Reduction E.g. 212: Multilevel optimization transformations <Ans.> BCF BCE ABF ABE ABCD H BCDEF ADF ADE ACF ACE G ) ( ) )( ( )) ( ) ( ( ) ( B A EF B D C A BCDEF F E D C A BCDEF F E D F E C A BCDEF DF DE CF CE A BCDEF ADF ADE ACF ACE G F E CD 2 1
86 J.J. Shann 286 (Cont d) C A F E CD )) )( ( ) ( ( )) ( ) ( ( ) ( F E C A CD A B F E C F E A ACD B CF CE AF AE ACD B BCF BCE ABF ABE ABCD H ( 2) A B H B A G extraction of G & H: substitution:
87 J.J. Shann 287 BCF BCE ABF ABE ABCD H BCDEF ADF ADE ACF ACE G ( 2) A B H B A G C A F E CD 3 2 1
88 Key to successful transformations: is the determination of the factors to be used in decomposition or extraction and choice of the transformation sequence to apply J.J. Shann 288
89 B. Transformation for Delay Reduction Define: Path delay the length of time it takes for a change in a signal to propagate down a path through the gates Define: Critical path the longest path(s) through a ckt Situation: In a large proportion of designs, the length of the longest path(s) through the ckt is often constrained. The # of gates in series may need to be reduced. Critical path gate elimination transformation J.J. Shann 289
90 Elimination transform: replaces intermediate variables, i, w/ the expressions on their right hand sides or removes other factoring of some variables Reduces the # of gates in series Determination of factor or combination of factors to be eliminated: while watching for the effect of increasing gate input count the increase in gate input count for the combinations of eliminations that reduce the problem path lengths by at lease one gate are of interest Reducing both path length and gate input count often cannot be achieved simultaneously J.J. Shann 290
91 Example 213 E.g.: Transformation for delay reduction Assumption: Ignore the delay of NOT gate. G A 1 2 B 1 2 H B( A 1 3 2) CD E F A C GIC 25 J.J. Shann 291
92 G A 1 H B( A 1 3 2) 1 CD 2 E F GIC 25 3 A C <Ans.> 3 combinations of eliminations that reduce 1 gate delay: i. removal of the factor B in H GIC increases 0 and H path length reduced ii. removal of the intermediate variables 1, 2, 3 GIC increases 20 (?) and H path length further reduced iii. removal of B, 1, 2, 3 GIC increases 23 (?) and H path length again reduced 2 B 1 2 G A 1 H B A 1 2 B B 3 1 G ACE ACF ADE ADF BCDEF H B( ACD AE AF CE CF) G ACE ACF ADE ADF BCDEF H ABCD ABE ABF BCE BCF CD E F A C J.J. Shann 292
93 J.J. Shann B BA H B A G ( 2) A B H B A G C A F E CD Eliminate the factor B
94 27 Other Gate Types Basic logic operations: AND, OR, NOT All possible functions of n binary variables: n binary variables 2 n distinct minterms 2 2n possible functions E.g.: n 2 4 minterms 16 possible functions J.J. Shann 294
95 J.J. Shann 295
96 The 16 functions can be subdivided into 3 categories: 1. 2 functions that produce a constant 0 or functions w/ unary operations complement (NOT) and transfer functions w/ binary operators that define eight different operations AND, OR, NAND, NOR, exclusiveor, equivalence, inhibition, and implication. J.J. Shann 296
97 Digital Logic Gates Boolean expression: AND, OR and NOT operations It is easier to implement a Boolean function in these types of gates. Consider the construction of other types of logic gates: the feasibility and economy of implementing the gate w/ electronic components the basic properties of the binary operations E.g.: commutativity, associativity, the ability of the gate to implement Boolean functions alone or in conjunction w/ other gates the convenience of representing gate functions that are frequently used J.J. Shann 297
98 AND OR Primitive Digital Logic Gates NOT (inverter) Buffer amplify an electrical signal to permit more gates to be attached to the output or to decrease the time it takes for signals to propagate through the ckt 3state Buffer ( 29) NAND NOR J.J. Shann 298
99 Define: Universal gate a gate type that alone can be used to implement all Boolean functions E.g.: NAND gate, NOR gate Proof of a universal gate: Show that the logical ops of AND, OR, and NOT can be obtained w/ the universal gate only. E.g.: Show that the NAND gate is a universal gate J.J. Shann 299
100 E.g.: Show that the NAND gate is a universal gate J.J. Shann 2100
101 E.g.: Simplify the Boolean function and implement it by NAND gates <Ans.> F(, Y, Z) m(0,2,4,5,6) Y Z J.J. Shann 2101
102 Method 1: Y Z AND OR Y Z Y Z J.J. Shann 2102
103 Method 2: Y Z Y Z Y Z J.J. Shann 2103
104 Complex Digital Logic Gates ExclusiveOR ( 28) NOR ( 28) ANDORInvert (AOI) the complement of SoP E.g.: 21 AOI F Y Z E.g.: AOI F TUV W YZ ORANDInvert (OAI) the dual of AOI the complement of PoS ANDOR (AO) ORAND (OA) J.J. Shann 2104
105 Adv. of using complex gates: reduce the ckt complexity needed for implementing specific Boolean functions in order to reduce integrated ckt (IC) cost reduce the time required for signals to propagate through a ckt J.J. Shann 2105
106 28 ExclusiveOR Operator and Gates ExclusiveOR: OR, Y Y is equal to 1 if exactly one input variable is equal to 1 ExclusiveNOR: NOR, also called equivalence Y Y Y Y is equal to 1 if both and Y are equal to 1 or if both are equal to 0. OR & NOR are the complement to each other. Y Y Y ( Y )( Y ) Y Y They are particularly useful in arithmetic operations and errordetection and correction ckts. J.J. Shann 2106
107 Properties of OR Identities: Y Y Y Y can be verified by using a truth table or by replacing the op by its equivalent Boolean expression Commutativity and associativity: A B B A (A B) C A (B C) A B C OR gates w/ three or more inputs J.J. Shann 2107
108 Implementations of OR function OR function is usually constructed w/ other types of gates: J.J. Shann 2108
109 Odd Function Multiplevariable OR operation: odd function equal to 1 if the input variables have an odd # of 1 s E.g.: 3variable OR Y Z ( Y Y ) Z ( Y Y ) Z ( Y Y ) Z Y Z Y Z YZ YZ m(1,2,4,7) is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1. J.J. Shann 2109
110 E.g.: 4variable OR A B C D (AB A B) (CD C D) (AB A B)(CD C D ) (AB A B )(CD C D) Σ(1, 2, 4, 7, 8, 11, 13, 14) nvariable OR function: the logical sum of the 2 n /2 minterms whose binary numerical values have an odd # of 1 s. J.J. Shann 2110
111 Even Function Multiplevariable NOR op: an even function E.g.: 4variable NOR nvariable NOR function: the logical sum of the 2 n /2 minterms whose binary numerical values have an even # of 1 s. J.J. Shann 2111
112 Logic Diagram of Odd & Even Functions Logic diagram of odd & even functions: Multipleinput Odd function: J.J. Shann 2112
113 Example Simplify the Boolean function and implement it by OR gates and other gates F(W,, Y, Z) Σ(1, 4, 7, 8, 13) <Ans.> YZ W F Y (W Z) WZ ( Y) or Y (W Z) W YZ or Y (W Z) W YZ J.J. Shann 2113
114 29 HighImpedance Outputs Output values of a gate may be: 0 or 1, as usual; plus HiZ: highimpedance state behaves as an open ckt, i.e., looking back into the ckt, the output appears to be disconnected * Where can this be useful? Gates w/ only logic 0 and 1 outputs cannot have their outputs connected together. * Gates w/ HiZ output values can have their outputs connected together, provided that no 2 gates drive the line at the same time to opposite 0 and 1 values. Structures that provide HiZ: 3state buffers or others transmission gates J.J. Shann 2114
115 ThreeState Buffers 3state buffer: J.J. Shann 2115
116 Multiplexer constructed by 3 state buffers: E.g.: 2to1 MU Input 0 Input 1 MU Output Selection input J.J. Shann 2116
117 Transmission Gates Transmission gate (TG): J.J. Shann 2117
118 OR gate constructed from transmission gates: J.J. Shann 2118
119 210 Chapter Summary Primitive logic ops: AND, OR, NOT Boolean algebra Minterm & maxterm standard forms SoP and PoS standard forms 2level gate ckts 2 cost measures for ckt optimization: # of input literals to a ckt total # of inputs to the gates in a ckt J.J. Shann 2119
120 Circuit optimization: 2level ckt optimization Boolean algebra manipulation Kmap QuineMcCluskey method Multilevel ckt optimization Other logic gates: NAND, NOR OR, NOR HiZ outputs: 3state buffer transmission gates J.J. Shann 2120
IT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationCombinational Logic Circuits Part III Theoretical Foundations
Combinational Logic Circuits Part III Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationUnitIV Boolean Algebra
UnitIV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8 Terminology For
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More informationDigital Logic Design (CEN120) (3+1)
Digital Logic Design (CEN120) (3+1) ASSISTANT PROFESSOR Engr. Syed Rizwan Ali, MS(CAAD)UK, PDG(CS)UK, PGD(PM)IR, BS(CE)PK HEC Certified Master Trainer (MTFPDP) PEC Certified Professional Engineer (COM/2531)
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design JieHong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps Kmap Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/kmapswalksandgraycodes/
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationBoolean algebra. June 17, Howard Huang 1
Boolean algebra Yesterday we talked about how analog voltages can represent the logical values true and false. We introduced the basic Boolean operations AND, OR and NOT, which can be implemented in hardware
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationBoolean Algebra. BME208 Logic Circuits Yalçın İŞLER
Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +
More informationKarnaugh Map (KMap) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using Kmap
Karnaugh Map (KMap) Ch. 2.4 Ch. 2.5 Simplification using Kmap A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationUNIT 2 BOOLEAN ALGEBRA
UNIT 2 BOOLEN LGEBR Spring 2 2 Contents Introduction Basic operations Boolean expressions and truth tables Theorems and laws Basic theorems Commutative, associative, and distributive laws Simplification
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/404. Seq. Circuit Behavior. Outline.
Review EECS 150  Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 9404 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow
More information(Refer Slide Time 6:48)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture  8 Karnaugh Map Minimization using Maxterms We have been taking about
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationComputer Science. Unit4: Introduction to Boolean Algebra
Unit4: Introduction to Boolean Algebra Learning Objective At the end of the chapter students will: Learn Fundamental concepts and basic laws of Boolean algebra. Learn about Boolean expression and will
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Twolevel Optimization Manipulating a function until it is
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flipflops Functional bocks: Combinational, Sequential Instruction
More informationBinary logic. Dr.AbuArqoub
Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible
More informationPoints Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions SumofProducts (SOP),
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationSwitching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION
Switching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION Twovariable kmap: A twovariable kmap can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,
More information4 KARNAUGH MAP MINIMIZATION
4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the
More informationLecture 5. Chapter 2: Sections 47
Lecture 5 Chapter 2: Sections 47 Outline Boolean Functions What are Canonical Forms? Minterms and Maxterms Index Representation of Minterms and Maxterms SumofMinterm (SOM) Representations ProductofMaxterm
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More informationCh. 5 : Boolean Algebra &
Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying
More informationLecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationNODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY
No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra
More informationMenu. Algebraic Simplification  Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification
Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification  Boolean Algebra Minterms (written as m i ):
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More informationCircuit analysis summary
Boolean Algebra Circuit analysis summary After finding the circuit inputs and outputs, you can come up with either an expression or a truth table to describe what the circuit does. You can easily convert
More informationUNIT V COMBINATIONAL LOGIC DESIGN
UNIT V COMBINATIONAL LOGIC DESIGN NOTE: This is UNITV in JNTUK and UNITIII and HALF PART OF UNITIV in JNTUA SYLLABUS (JNTUK)UNITV: Combinational Logic Design: Adders & Subtractors, Ripple Adder, Look
More informationIntroduction. The QuineMcCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick
CSEE E6861y Prof. Steven Nowick The QuineMcCluskey Method Handout 5 January 24, 2013 Introduction The QuineMcCluskey method is an exact algorithm which finds a minimumcost sumofproducts implementation
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationChap2 Boolean Algebra
Chap2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationMODULE 5  COMBINATIONAL LOGIC
Introduction to Digital Electronics Module 5: Combinational Logic 1 MODULE 5  COMBINATIONAL LOGIC OVERVIEW: For any given combination of input binary bits or variables, the logic will have a specific
More informationAnnouncements. Chapter 2  Part 1 1
Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this
More information